| PIC16F1786 | ||||
|---|---|---|---|---|
| CONFIG1 (address:0x8007, mask:0xFFFF) | ||||
| FOSC -- Oscillator Selection | ||||
| FOSC = LP | 0xFFF8 | LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins. | ||
| FOSC = XT | 0xFFF9 | XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins. | ||
| FOSC = HS | 0xFFFA | HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins. | ||
| FOSC = EXTRC | 0xFFFB | EXTRC oscillator: External RC circuit connected to CLKIN pin. | ||
| FOSC = INTOSC | 0xFFFC | INTOSC oscillator: I/O function on CLKIN pin. | ||
| FOSC = ECL | 0xFFFD | ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pin. | ||
| FOSC = ECM | 0xFFFE | ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pin. | ||
| FOSC = ECH | 0xFFFF | ECH, External Clock, High Power Mode (4-32 MHz): device clock supplied to CLKIN pin. | ||
| WDTE -- Watchdog Timer Enable | ||||
| WDTE = OFF | 0xFFE7 | WDT disabled. | ||
| WDTE = SWDTEN | 0xFFEF | WDT controlled by the SWDTEN bit in the WDTCON register. | ||
| WDTE = NSLEEP | 0xFFF7 | WDT enabled while running and disabled in Sleep. | ||
| WDTE = ON | 0xFFFF | WDT enabled. | ||
| PWRTE -- Power-up Timer Enable | ||||
| PWRTE = ON | 0xFFDF | PWRT enabled. | ||
| PWRTE = OFF | 0xFFFF | PWRT disabled. | ||
| MCLRE -- MCLR Pin Function Select | ||||
| MCLRE = OFF | 0xFFBF | MCLR/VPP pin function is digital input. | ||
| MCLRE = ON | 0xFFFF | MCLR/VPP pin function is MCLR. | ||
| CP -- Flash Program Memory Code Protection | ||||
| CP = ON | 0xFF7F | Program memory code protection is enabled. | ||
| CP = OFF | 0xFFFF | Program memory code protection is disabled. | ||
| CPD -- Data Memory Code Protection | ||||
| CPD = ON | 0xFEFF | Data memory code protection is enabled. | ||
| CPD = OFF | 0xFFFF | Data memory code protection is disabled. | ||
| BOREN -- Brown-out Reset Enable | ||||
| BOREN = OFF | 0xF9FF | Brown-out Reset disabled. | ||
| BOREN = SBODEN | 0xFBFF | Brown-out Reset controlled by the SBOREN bit in the BORCON register. | ||
| BOREN = NSLEEP | 0xFDFF | Brown-out Reset enabled while running and disabled in Sleep. | ||
| BOREN = ON | 0xFFFF | Brown-out Reset enabled. | ||
| CLKOUTEN -- Clock Out Enable | ||||
| CLKOUTEN = ON | 0xF7FF | CLKOUT function is enabled on the CLKOUT pin. | ||
| CLKOUTEN = OFF | 0xFFFF | CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin. | ||
| IESO -- Internal/External Switchover | ||||
| IESO = OFF | 0xEFFF | Internal/External Switchover mode is disabled. | ||
| IESO = ON | 0xFFFF | Internal/External Switchover mode is enabled. | ||
| FCMEN -- Fail-Safe Clock Monitor Enable | ||||
| FCMEN = OFF | 0xDFFF | Fail-Safe Clock Monitor is disabled. | ||
| FCMEN = ON | 0xFFFF | Fail-Safe Clock Monitor is enabled. | ||
| CONFIG2 (address:0x8008, mask:0xFFFF) | ||||
| WRT -- Flash Memory Self-Write Protection | ||||
| WRT = ALL | 0xFFFC | 000h to 7FFh write protected, no addresses may be modified by EECON control. | ||
| WRT = HALF | 0xFFFD | 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control. | ||
| WRT = BOOT | 0xFFFE | 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control. | ||
| WRT = OFF | 0xFFFF | Write protection off. | ||
| VCAPEN -- Voltage Regulator Capacitor Enable bit | ||||
| VCAPEN = ON | 0xFFDF | Vcap functionality is enabled on RA6 (Vddcore is connected to the pad). | ||
| VCAPEN = OFF | 0xFFFF | Vcap functionality is disabled on RA6. | ||
| PLLEN -- PLL Enable | ||||
| PLLEN = OFF | 0xFEFF | 4x PLL disabled. | ||
| PLLEN = ON | 0xFFFF | 4x PLL enabled. | ||
| STVREN -- Stack Overflow/Underflow Reset Enable | ||||
| STVREN = OFF | 0xFDFF | Stack Overflow or Underflow will not cause a Reset. | ||
| STVREN = ON | 0xFFFF | Stack Overflow or Underflow will cause a Reset. | ||
| BORV -- Brown-out Reset Voltage Selection | ||||
| BORV = HI | 0xFBFF | Brown-out Reset Voltage (Vbor), high trip point selected. | ||
| BORV = LO | 0xFFFF | Brown-out Reset Voltage (Vbor), low trip point selected. | ||
| LPBOR -- Low Power Brown-Out Reset Enable Bit | ||||
| LPBOR = ON | 0xF7FF | Low power brown-out is enabled. | ||
| LPBOR = OFF | 0xFFFF | Low power brown-out is disabled. | ||
| LVP -- Low-Voltage Programming Enable | ||||
| LVP = OFF | 0xDFFF | High-voltage on MCLR/VPP must be used for programming. | ||
| LVP = ON | 0xFFFF | Low-voltage programming enabled. | ||
This page generated automatically by the device-help.pl program (2013-08-01 15:50:27 UTC) from the 8bit_device.info file (rev: 1.14) of mpasmx and from the gputils source package (rev: svn 983:985). The mpasmx is included in the MPLAB X.