| #xxxxxxb |
#xxh |
description |
occurence/duration |
| 0000000b |
00h |
data reads |
occurence |
| 0000001b |
01h |
data writes |
occurence |
| 0000010b |
02h |
data TLB misses |
occurence |
| 0000011b |
03h |
data read misses |
occurence |
| 0000100b |
04h |
data write misses |
occurence |
| 0000101b |
05h |
writes (hits) to M or E state lines |
occurence |
| 0000110b |
06h |
data cache lines written back |
occurence |
| 0000111b |
07h |
data cache snoops |
occurence |
| 0001000b |
08h |
data cache snoop hits |
occurence |
| 0001001b |
09h |
memory accesses in both pipes |
occurence |
| 0001010b |
0Ah |
bank conflicts |
occurence |
| 0001011b |
0Bh |
misaligned data memory references |
occurence |
| 0001100b |
0Ch |
code reads |
occurence |
| 0001101b |
0Dh |
code TLB misses |
occurence |
| 0001110b |
0Eh |
code cache misses |
occurence |
| 0001111b |
0Fh |
any segment register loaded |
occurence |
| 0010000b |
10h |
reserved |
| 0010001b |
11h |
reserved |
| 0010010b |
12h |
branches |
occurence |
| 0010011b |
13h |
BTB hits |
occurence |
| 0010100b |
14h |
taken branches or BTB hits |
occurence |
| 0010101b |
15h |
pipeline flushes |
occurence |
| 0010110b |
16h |
instructions executed in both pipes |
occurence |
| 0010111b |
17h |
instructions executed in the Y-pipe |
occurence |
| 0011000b |
18h |
clocks while bus cycle in progress (bus utilization) |
duration |
| 0011001b |
19h |
pipe stalled by full write buffers (writes backup) |
duration |
| 0011010b |
1Ah |
pipe stalled by waiting for data memory reads |
duration |
| 0011011b |
1Bh |
pipe stalled by writes to not-M or not-E lines |
duration |
| 0011100b |
1Ch |
locked bus cycles |
occurence |
| 0011101b |
1Dh |
I/O read or write cycles |
occurence |
| 0011110b |
1Eh |
non-cacheable memory references |
occurence |
| 0011111b |
1Fh |
pipeline stalled by address generation interlock |
duration |
| 0100000b |
20h |
reserved |
| 0100001b |
21h |
reserved |
| 0100010b |
22h |
floating-point operations |
occurence |
| 0100011b |
23h |
breakpoint matches on DR0 register |
occurence |
| 0100100b |
24h |
breakpoint matches on DR1 register |
occurence |
| 0100101b |
25h |
breakpoint matches on DR2 register |
occurence |
| 0100110b |
26h |
breakpoint matches on DR3 register |
occurence |
| 0100111b |
27h |
hardware interrupts |
occurence |
| 0101000b |
28h |
data reads or data writes |
occurence |
| 0101001b |
29h |
data read misses or data write misses |
occurence |
| 0101010b |
2Ah |
reserved |
| reserved |
| 0101011b |
2Bh |
MMX instructions executed in X-pipe |
occurence |
| MMX instructions executed in Y-pipe |
occurence |
| 0101100b |
2Ch |
reserved |
| reserved |
| 0101101b |
2Dh |
EMMS instructions executed |
occurence |
| transition between MMX and FP instructions |
occurence |
| 0101110b |
2Eh |
reserved |
| reserved |
| 0101111b |
2Fh |
saturating MMX instructions executed |
occurence |
| saturations performed |
occurence |
| 0110000b |
30h |
reserved |
| reserved |
| 0110001b |
31h |
MMX instruction data reads |
occurence |
| reserved |
| 0110010b |
32h |
reserved |
| taken branches |
occurence |
| 0110011b |
33h |
reserved |
| reserved |
| 0110100b |
34h |
reserved |
| reserved |
| 0110101b |
35h |
reserved |
| reserved |
| 0110110b |
36h |
reserved |
| reserved |
| 0110111b |
37h |
returns, predicted incorrectly or not predicted at all |
occurence |
| returns, predicted (correctly and incorrectly) |
occurence |
| 0111000b |
38h |
MMX instruction multiply unit interlock |
duration |
| MOVD/MOVQ store stall due to previous operation |
duration |
| 0111001b |
39h |
returns |
occurence |
| RSB (return stack buffer) overflows |
occurence |
| 0111010b |
3Ah |
BTB false entries |
occurence |
| BTB miss prediction on a not taken branch |
occurence |
| 0111011b |
3Bh |
stalled due to full write buffers while executing MMX instruction |
duration |
| stall on MMX instruction write to E or M line |
duration |
| 0111100b |
3Ch |
reserved |
| 0111101b |
3Dh |
reserved |
| 0111110b |
3Eh |
reserved |
| 0111111b |
3Fh |
reserved |
| 1000000b |
40h |
L2 TLB misses (code or data) |
occurence |
| 1000001b |
41h |
L1 TLB data miss |
occurence |
| 1000010b |
42h |
L1 TLB code miss |
occurence |
| 1000011b |
43h |
L1 TLB miss (code or data) |
occurence |
| 1000100b |
44h |
TLB flushes |
occurence |
| 1000101b |
45h |
TLB page invalidates |
occurence |
| 1000110b |
46h |
TLB page invalidates that hit |
occurence |
| 1000111b |
47h |
reserved |
| 1001000b |
48h |
instructions decoded |
occurence |
1001001b ... 1111111b |
49h ... 7Fh |
reserved |
| note |
Depending on which counter is used for the events 2A..3Fh, two different
events are counted on Cyrix M2 processors. The first listed event is for
counter #0, while the second one is for counter #1. Notice that Cyrix tried
to use the same events which are defined on Intel P5 processors, but added
one more bit in the CESR.ES0/1 fields, allowing for more events (above 3Fh).
|