| name |
description |
states |
| MASK |
increment limit |
limit 00..FFh (counter will be incremented if this limit was reached or exceeded) #1 |
| INV |
invert MASK |
1=increment if <=MASK increments #1 |
0=increment if >=MASK increments #1 |
| EN |
enable counter #2 |
1=both counters are enabled |
0=both counters are disabled |
| INT |
enable interrupt #3 |
1=overflow causes APIC interrupt |
0=overflow doesn't cause APIC interrupt |
| PC |
PM1/0 pin control |
1=pin indicates counter overflows |
0=pin indicates counter increments |
| E |
edge detect |
1=count clocks |
0=count events |
| OS |
count OS |
1=enable counting for CPL=0 |
0=disable counting for CPL=0 |
| US |
count user |
1=enable counting for CPL=1..3 |
0=disable counting for CPL=1..3 |
| UNIT |
unit mask select |
unit mask # (see notes for P6 and K7) |
| ES |
event select |
event # (00..FFh for P6, K7, and VIA Cyrix III) |
| notes |
description |
| #1 |
This allows counting multiple events ("increment if at least xxh/cycle" or "increment if less than xxh/cycle"). |
| #2 |
This bit is present in CESR#0 only. (Disable a single counter by selecting OS=0 and US=0.) |
| #3 |
A local APIC interrupt will be generated. |